When people talk about SSD performance, they usually talk about speed numbers.
But inside an SSD, a write operation is not a simple \u201cdata in, data stored\u201d process.<\/p>\n
In reality, every write passes through multiple internal stages<\/strong>, each of which affects performance, endurance, and long-term stability.<\/p>\n Understanding this internal flow explains:<\/p>\n why short benchmarks look impressive<\/p>\n<\/li>\n why sustained writes slow down<\/p>\n<\/li>\n and where write amplification actually comes from<\/p>\n<\/li>\n<\/ul>\n A write operation inside an SSD typically follows this sequence:<\/p>\n Host \u2192 Controller \u2192 DRAM Cache \u2192 NAND Flash<\/strong><\/p>\n Each step serves a purpose \u2014 and each introduces trade-offs.<\/p>\n The host system (OS or application) sends write commands through SATA or PCIe. The SSD controller\u2019s first job is not writing data \u2014 The controller translates logical block addresses (LBAs) into physical NAND locations using the Flash Translation Layer (FTL).<\/p>\n At this stage, the controller:<\/p>\n groups small random writes<\/p>\n<\/li>\n schedules them across multiple NAND channels<\/p>\n<\/li>\n decides when to erase old blocks<\/p>\n<\/li>\n<\/ul>\n None of this is visible in benchmarks \u2014 but it defines real performance.<\/p>\n Before data reaches NAND, it usually lands in DRAM cache<\/strong>.<\/p>\n This DRAM is used to:<\/p>\n store mapping tables<\/p>\n<\/li>\n merge small writes into larger chunks<\/p>\n<\/li>\n reduce immediate NAND writes<\/p>\n<\/li>\n<\/ul>\n This is why many SSDs appear extremely fast at first \u2014 Once the cache fills or flushes, behavior changes.<\/p>\n NAND flash cannot overwrite data directly.<\/p>\n Each write requires:<\/p>\n Reading existing data<\/p>\n<\/li>\n Modifying it<\/p>\n<\/li>\n Erasing entire blocks<\/p>\n<\/li>\n Writing new pages<\/p>\n<\/li>\n<\/ol>\n This is where physical limits appear \u2014 and where performance slows down.<\/p>\n Write amplification happens when the SSD writes more data internally<\/strong> than the host requested.<\/p>\n NAND requires block-level erase<\/p>\n<\/li>\n Small random writes force read\u2013modify\u2013write cycles<\/p>\n<\/li>\n Garbage collection moves valid data repeatedly<\/p>\n<\/li>\n<\/ul>\n This invisible extra work:<\/p>\n increases latency<\/p>\n<\/li>\n consumes endurance<\/p>\n<\/li>\n raises internal temperature<\/p>\n<\/li>\n<\/ul>\n Write amplification is not a flaw \u2014 Most SSD benchmarks:<\/p>\n run for seconds, not hours<\/p>\n<\/li>\n use empty drives<\/p>\n<\/li>\n focus on burst writes<\/p>\n<\/li>\n<\/ul>\n In this phase:<\/p>\n data fits inside DRAM or SLC cache<\/p>\n<\/li>\n garbage collection is minimal<\/p>\n<\/li>\n NAND is fresh and unfragmented<\/p>\n<\/li>\n<\/ul>\n \uacb0\uacfc: During sustained writes:<\/p>\n DRAM cache fills<\/p>\n<\/li>\n SLC cache converts back to TLC \/ QLC<\/p>\n<\/li>\n garbage collection becomes active<\/p>\n<\/li>\n NAND erase cycles accumulate<\/p>\n<\/li>\n<\/ul>\n This is when:<\/p>\n write speed drops sharply<\/p>\n<\/li>\n latency becomes inconsistent<\/p>\n<\/li>\n thermal throttling may appear<\/p>\n<\/li>\n<\/ul>\n Two SSDs with similar benchmark scores can behave very differently<\/strong> here.<\/p>\n This gap explains why:<\/p>\n content creation<\/p>\n<\/li>\n logging systems<\/p>\n<\/li>\n database workloads<\/p>\n<\/li>\n<\/ul>\n often expose weaknesses that benchmarks never show.<\/p>\n For OEMs, understanding write behavior is critical because:<\/p>\n failures appear late<\/p>\n<\/li>\n performance degradation is gradual<\/p>\n<\/li>\n instability is workload-dependent<\/p>\n<\/li>\n<\/ul>\n Selecting an SSD based only on peak write speed ignores:<\/p>\n cache exhaustion behavior<\/p>\n<\/li>\n long-term write amplification<\/p>\n<\/li>\n thermal and power stress<\/p>\n<\/li>\n<\/ul>\n Stable systems are built by matching SSD behavior to real workloads<\/strong>, not benchmark charts.<\/p>\n An SSD write is not a single action \u2014 Short benchmarks show what an SSD can do briefly. Understanding this difference is the foundation for:<\/p>\n correct SSD selection<\/p>\n<\/li>\n realistic performance expectations<\/p>\n<\/li>\n and long-term system stability<\/p>\n<\/li>\n<\/ul>\n At Oreton, SSD validation focuses on sustained behavior, consistency, and workload realism \u2014 because how an SSD writes over time matters far more than how fast it writes once.<\/p>","protected":false},"excerpt":{"rendered":" \uc2e4\uc81c \uc4f0\uae30 \ub3d9\uc791\uc774 \ubca4\uce58\ub9c8\ud06c\uc640 \ub2e4\ub978 \uc774\uc720 SSD \uc131\ub2a5\uc5d0 \ub300\ud574 \uc774\uc57c\uae30\ud560 \ub54c \ubcf4\ud1b5 \uc18d\ub3c4 \uc218\uce58\uc5d0 \ub300\ud574 \uc774\uc57c\uae30\ud558\uc9c0\ub9cc SSD \ub0b4\ubd80\uc5d0\uc11c \uc4f0\uae30 \uc791\uc5c5\uc740 \ub2e8\uc21c\ud55c \"\ub370\uc774\ud130 \uc785\ub825, \ub370\uc774\ud130 \uc800\uc7a5\" \ud504\ub85c\uc138\uc2a4\uac00 \uc544\ub2d9\ub2c8\ub2e4. \uc2e4\uc81c\ub85c \ubaa8\ub4e0 \uc4f0\uae30\ub294 \uc5ec\ub7ec \ub0b4\ubd80 \ub2e8\uacc4\ub97c \uac70\uce58\uba70, \uac01 \ub2e8\uacc4\ub294 \uc131\ub2a5, \ub0b4\uad6c\uc131 \ubc0f \uc7a5\uae30\uc801\uc778 \uc548\uc815\uc131\uc5d0 \uc601\ud5a5\uc744 \ubbf8\uce69\ub2c8\ub2e4. \uc774\ub97c \uc774\ud574\ud558\uba74...<\/p>","protected":false},"author":3,"featured_media":3589,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-3587","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog"],"yoast_head":"\n\n
\n1. The Real Write Path Inside an SSD<\/h2>\n
1\ufe0f\u20e3 Host to Controller<\/h3>\n
These commands arrive out of order<\/strong>, in small blocks, and often mixed with reads.<\/p>\n
it is organizing chaos<\/strong>.<\/p>\n
\n2\ufe0f\u20e3 Controller Logic: Translation and Scheduling<\/h3>\n
\n
\n3\ufe0f\u20e3 DRAM Cache: The Critical Buffer<\/h3>\n
\n
you are often writing to DRAM, not NAND<\/strong>.<\/p>\n
\n4\ufe0f\u20e3 NAND Flash: The Slow, Permanent Step<\/h3>\n
\n
\n2. Where Write Amplification Comes From<\/h2>\n
Why It Happens<\/h3>\n
\n
A Simple Example<\/h3>\n
\n\n
\n \nHost Writes<\/th>\n Actual NAND Writes<\/th>\n<\/tr>\n<\/thead>\n \n 10 GB<\/td>\n 15\u201330 GB<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<\/div>\n \n
it is a structural reality of flash memory<\/strong>.<\/p>\n
\n3. Why Short Benchmarks Look So Good<\/h2>\n
\n
\n
\ud83d\udc49 peak numbers that users rarely see again.<\/p>\n
\n4. Why Sustained Writes Behave Completely Differently<\/h2>\n
\n
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\n5. Sustained Write vs Burst Write: A Practical Comparison<\/h2>\n
\n\n
\n \n\uc2dc\ub098\ub9ac\uc624<\/th>\n Short Benchmark<\/th>\n Sustained Real Workload<\/th>\n<\/tr>\n<\/thead>\n \n Cache usage<\/td>\n Mostly DRAM \/ SLC<\/td>\n Mostly NAND<\/td>\n<\/tr>\n \n \uc4f0\uae30 \uc99d\ud3ed<\/td>\n \ub0ae\uc74c<\/td>\n \ub192\uc74c<\/td>\n<\/tr>\n \n Temperature<\/td>\n \ub0ae\uc74c<\/td>\n Rising<\/td>\n<\/tr>\n \n Speed stability<\/td>\n \ub9e4\uc6b0 \ub192\uc74c<\/td>\n Highly variable<\/td>\n<\/tr>\n \n Endurance impact<\/td>\n Minimal<\/td>\n Significant<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<\/div>\n \n
\n6. Why This Matters for OEM and System Design<\/h2>\n
\n
\n
\nConclusion: Writing to an SSD Is a Process, Not a Number<\/h2>\n
it is a pipeline of buffering, translation, scheduling, and physical limitations.<\/p>\n
Real workloads reveal how it behaves over time.<\/p>\n\n